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References

1
A. V. Aho, R. Sethi, and J. D. Ullman. Compilers - Principles, Techniques, and Tools. Addison-Wesley, 1986.

2
R. Arnold, F. Mueller, D. B. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. In IEEE Real-Time Systems Symposium, pages 172-181, December 1994.

3
M. E. Benitez and J. W. Davidson. A portable global optimizer and linker. In ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 329-338, June 1988.

4
UC Berkeley CS. CPU info center. http://infopad.eecs.
berkeley.edu/CIC/summary/local, March 1997.

5
J. W. Davidson and D. B. Whalley. A design environment for addressing architecture and compiler interactions. Microprocessors and Microsystems, 15(9):459-472, November 1991.

6
C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In IEEE Real-Time Systems Symposium, pages 288-297, December 1995.

7
J. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 2nd edition, 1996.

8
Y. Hur, Y. H. Bea, S.-S. Lim, B.-D. Rhee, S. L. Min, Y. C. Park, M. Lee, H. Shin, and C. S. Kim. Worst case timing analysis of RISC processors: R3000/R3010 case study. In IEEE Real-Time Systems Symposium, pages 308-319, December 1995.

9
S. Kim, S. Min, and R. Ha. Efficient worst case timing analysis of data caching. In IEEE Real-Time Technology and Applications Symposium, June 1996.

10
Y.-T. S. Li, S. Malik, and A. Wolfe. Efficient microarchitecture modeling and path analysis for real-time software. In IEEE Real-Time Systems Symposium, pages 298-397, December 1995.

11
Y.-T. S. Li, S. Malik, and A. Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction caches. In IEEE Real-Time Systems Symposium, December 1996.

12
S.-S. Lim, Y. H. Bea, G. T. Jang, B.-D. Rhee, S. L. Min, Y. C. Park, H. Shin, and C. S. Kim. An accurate worst case timing analysis for RISC processors. In IEEE Real-Time Systems Symposium, pages 97-108, December 1994.

13
F. Mueller. Static Cache Simulation and its Applications. PhD dissertation, Dept. of Computer Science, Florida State University, July 1994.

14
F. Mueller. Generalizing timing predictions to set-associative caches. In EuroMicro Real-Time Workshop, June 1997.

15
Texas Instruments. TMS390S10 Integrated SPARC Processor, February 1993.

16
R. White. Bounding Worst-Case Data Cache Performance. PhD dissertation, Dept. of Computer Science, Florida State University, April 1997.



Robert Palmer
Mon May 19 10:18:36 EDT 1997