There are several areas of timing analysis that can be further investigated. The effect of wrap-around fill data caches can be analyzed. We currently assume that each load requires a constant miss penalty for accessing memory. However, cache lines are filled from memory one word at a time, and analyzing the wrap-around fill behavior can tighten the predicted WCET. Timing predictions for set-associative data caches can be produced in a manner similar to that for instruction caches described in this paper. Best case timing bounds for both data and set-associative caches may also be investigated. An eventual goal of this research is to integrate the timing analysis of both instruction and data caches to obtain timing predictions for a complete machine. Actual machine measurements using a logic analyzer could then be used to gauge the effectiveness of the entire timing analysis environment.