We believe that our work of a minimal hardware simulator for the purpose of cycle accounting is unprecedented. The simulation framework is being designed and implemented for the MicroSPARC I architecture but should be retargetable for other RISC architectures. The application to the debugging of real-time programs provides the means to test an embedded system on a regular workstation using simulation. This facilitates the process of debugging for the user. It supports queries for the elapsed (virtual) time, which can be used to relate debugging output to time information. Time distortion during debugging is minimized and deadlines can be monitored. Thus, a deadline miss can be located and the corresponding task may be tuned by determining where most of the time is spent. Alternatively, the task schedule can be redesigned to meet the deadline requirements. The minimal hardware simulation accounts for the effects of instruction caches and pipeline stalls. The effect of data caches is subject to future research.