Little attention has been paid to the specific needs of debugging real-time systems, although debugging is a central part of the software development cycle and may account for up to 50% of the development time. When debugging real-time applications, it is often necessary to relate the value of a variable to the elapsed time. Time distortion, due to the interference of a debugging tool, has to be minimized. Deadline monitoring should be supported to detect missed deadlines. External events need to be simulated and deadlines should be monitored during debugging.
In the absence of dedicated real-time debuggers, developers often fall back to hardware monitoring (e.g. logic analyzers) with limited capabilities or to hardware simulators, which degrades the application performance by about three orders of a magnitude. The simulation overhead of conventional hardware simulators is due to the necessity to capture the entire logic of a microprocessor and the interpretive nature of the simulation process.
We are proposing a framework for a debugger that permits debugging of real-time applications through non-interpretive, minimal hardware simulation. The environment addresses the issues of time distortion, deadline monitoring, and external events. The hardware simulation is limited to the aspects relevant to processor cycle accounting. These aspects include cache simulation, instruction frequency accounting, and processor pipeline simulation.