Based on the categorization of instruction references introduced in the previous section, a bit-encoding approach has been formulated. The intention of this approach is to provide better performance than uncached systems (as currently used in real-time systems) and better predictability over conventional caches with a moderate sacrifice in execution speed. A fetch-from-memory bit is encoded into the instruction format by dedicating a single bit position. If the bit is set in an instruction, then the instruction will be fetched from main memory. If the bit is not set, then the instruction will be fetched from cache.
During each cache reference, the fetch-from-memory bit is evaluated in parallel with the tag comparison, as shown in the Appendix. The following logic is used to resolve instruction fetch requests:
In the last subcase, a memory fetch is performed although the program line already resides in code. If the effect of such a memory fetch is only simulated to reduce bus contention, as proposed in an earlier version of the paper, it would be unpredictable whether an actual memory fetch occurs or not. Thus, bus contention may or may not occur. The current semantics forces a memory access such that bus contention can be predicted for any memory reference with a fetch-from-memory bit set if a data reference occurs at the same time.
The fetch-from-memory bit is set whenever the Static Cache Simulation categorizes an instruction as a conflict or an always-miss. Otherwise the bit is cleared. This is straight forward for always-hits. For first-misses, on the other hand, the cache look-up fails on the first reference and the program line is fetched from main memory. For any subsequent references to this address, the instruction is found in cache with the bit clear resulting in a cache hit and a one cycle access time. Thus, bit-encoding takes advantage of first-miss instructions.
If an instruction is in a function that has multiple instances and the
instruction has not been categorized the same in the different instances,
then the static simulator must decide whether or not to set the
fetch-from-memory bit.
Currently, the static simulator conservatively decides to fetch from memory
if one or more instances categorize the instruction as a miss or a conflict.
Otherwise, the bit is cleared.