The access logic for an instruction cache using the proposed bit-encoded approach is illustrated in Figure 4.
Figure 4: Access Logic for Bit-Encoded Approach
The instruction memory contains the cached instructions. It is accessed by using the index field to select the cache line and the offset field to select the instruction within that line. The tag memory contains the state bit and address tag for each cache line and is also accessed by using the index field. The match logic compares the tag of the instruction's physical address to the tag obtained by accessing the tag memory and verifies the state to ensure that the cache line is valid. In parallel, it also checks that the fetch-from-memory bit is clear. If any of these conditions are not met, then it informs the CPU to stall. The logic to request a main memory fetch or stall for the appropriate number of cycles is not shown in this figure.