Cache memories have often been disabled for critical real-time tasks to provide sufficient predictability for scheduling analysis. This paper shows that the behavior of instruction cache references can be predicted to a large extent prior to the execution of a program via the method of Static Cache Simulation. The cache simulator uses information provided by the back-end of a compiler to statically predict the cache behavior of 84-99% of the instructions. Furthermore, a fetch-from-memory bit has been proposed which is added to the instruction encoding. This approach provides a speedup in execution time by a factor of 3-8 over uncached systems without sacrificing the predictability of the program's worst-case execution time. The ability to predict the caching behavior of a large percentage of the instruction references (in a conventional cached system) or even all instruction references (using the fetch-from-memory bit) can be used to predict the execution time of large code segments on machines with instruction caches.
In summary, instruction cache behavior is sufficiently predictable to provide worst-case execution time predictions which are tight enough for scheduling analysis in a non-preemptive environment. Thus, the performance advantage of instruction caches can be exploited for critical real-time tasks by enabling either conventional or bit-encoded instruction caches.