- ...Behavior
- 1st revision June 26, 1994. This work was supported in part by the
Office of Naval Research under contract # N00014-94-1-0006
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- ...functions
- We will use the term function rather than
procedure, subroutine, subprogram, or other equivalent notions.
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- ...blocks
- A basic block is a sequence of
instructions where only the first instruction may be preceded by a
label and only the last instruction may be a transfer of control.
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- ...misses.
- This additional requirement is a correction to
the version of this paper published in the LCTS'94 workshop.
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- ...cycles.
- The semantics
has been changed for a set fetch-from-memory bit since the publication
in the LCTS'94 workshop.
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- ...cleared
- It is possible in such a situation
that the merged instruction could be safely classified as a first-miss and
have its bit cleared. An example of this situation is the first instruction
in block 8 of Figure 3. It is the authors' intention to analyze
the control flow to recognize these situations in the future.
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- ...respectively
- h'and m' are approximately the same as the
number of instructions executed with the fetch-from-memory bit clear
and set respectively with the exception of first-misses which are
counted as misses on the first reference and hits on subsequent
references.
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- ...n=9.
- The latency for a memory
fetch is assumed to be n=9 cycles, a cache look-up takes one cycle,
and thus a cache hit also consumes one cycle while a miss takes
n+1=10 cycles. These assumptions are described as realistic by
other researchers [, ]. A memory fetch in an uncached
system fetches exactly one instruction while a memory fetch in a
cached system fetches a line of 4 instructions. Fetching a line of
multiple instructions is typically accomplished through a wider bus
between cache and main memory for a cached system.
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